Senior Analog Design Layout Engineer

  • Job Reference: 45988107-2
  • Date Posted: 14 November 2017
  • Recruiter: Networkers
  • Location: Cambridge, Cambridgeshire
  • Salary: On Application
  • Sector: Engineering
  • Job Type: Contract
  • Start Date: ASAP
  • Duration: 3 months

Job Description

  • Responsible for layout design of a complex high-speed, low-noise mixed-signal IP in 16nm CMOS process
  • Hands-on block-level layout design and verification work, top-level IP floor-planning and integration, IC sign-off and tape-out
  • Work closely with analogue design team on IP floor-planning, trial layout design and parasitic extraction of critical structures. Propose circuit design changes
  • Co-ordinate layout design activities across multiple sites. Delegate block-level layout work when feasible
  • Collaborate with CAD, process technology, package design and digital Back End teams
  • Document own work and participate in design reviews
  • Experience in design of high-speed or RF layout in advanced CMOS processes.
    • 16nm FinFET experience an advantage.
    • High-speed ADC layout design experience an advantage.
  • Good understanding of high-speed and low-noise layout design techniques and requirements.
  • Experience in top-level integration and tape-outs.
  • Knowledge of semiconductor device physics and process technology.
  • Communicating effectively with circuit and layout designers.
  • Possible extension

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